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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
DESCRIPTION
The HCPL-3700 voltage/current threshold detection optocoupler consists of an AlGaAs LED connected to a threshold sensing input buffer IC which are optically coupled to a high gain darlington output. The input buffer chip is capable of controlling threshold levels over a wide range of input voltages with a single resistor. The output is TTL and CMOS compatible.
8 1
FEATURES
AC or DC input Programmable sense voltage Logic level compatibility Threshold guaranteed over temperature (0C to 70C) * OptoplanarTM construction for high common mode immunity * UL recognized (file # E90700) * * * * TRUTH TABLE (Positive Logic) Input H L Output L H
8 1
8 1
APPLICATIONS
* * * * * * Low voltage detection 5 V to 240 V AC/DC voltage sensing Relay contact monitor Current sensing Microprocessor Interface Industrial controls
A 0.1 F bypass capacitor must be connected between pins 8 and 5.
AC DC+
1 2 3 4
8 7 6 5
VCC NC VO GND
AC/DC POWER
RX HCPL-3700 LOGIC
DCAC
GND 1
GND 2
ABSOLUTE MAXIMUM RATINGS (No derating required up to 70C)
Parameter Storage Temperature Operating Temperature Lead Solder Temperature EMITTER Input Current Average Surge Transient Input Voltage (Pins 2-3) Input Power Dissipation Total Package Power Dissipation DETECTOR Output Current Supply Voltage Output Voltage (Average) (Pins 8-5) (Pins 6-5) (Note 4) (Note 3) IO VCC VO PO 30 (MAX) -0.5 to 20 -0.5 to 20 210 (MAX) mA V V mW (Note 1) (Note 2) 3 ms, 120 Hz Pulse Rate 10 s, 120 Hz Pulse Rate VIN PIN PT IIN Symbol TSTG TOPR TSOL Value -55 to +125 -40 to +85 260 for 10 sec 50 (MAX) 140 (MAX) 500 (MAX) -0.5 (MIN) 230 (MAX) 305 (MAX) V mW mW mA Units C C C
Output Power Dissipation
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
ELECTRICAL CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified)
Parameter Input Threshold Current Test Conditions (VIN = VTH+, VCC = 4.5 V) (VO = 0.4 V, IO 4.2 mA) (Note 5) (VIN = V2 - V3, Pins 1 & 4 Open) (VCC = 4.5 V, VO = 0.4 V) (Note 5) (IO 4.2 mA) (VIN = V2 - V3, Pins 1 & 4 Open) (VCC = 4.5 V, VO = 2.4 V) (Note 5) (IO 100 A) |VIN = V1 - V4| (Pins 2 & 3 Open) (VCC = 4.5 V, VO = 0.4 V) (Note 5) (IO 4.2 mA) |VIN = |V1 - V4| (Pins 2 & 3 Open) (VCC = 4.5 V, VO = 2.4 V) (Note 5) (IO 100 A) (IHYS = ITH+ - ITH-) (VHYS = VTH+ - VTH-) (VIHC1 = V2 - V3, V3 = GND) (IIN = 10 mA, Pins 1 & 4 Connected to Pin 3) (VIHC2 = |V1 - V4|) (|IIN| = 10 mA) (Pins 2 & 3 Open) (VIHC3 = V2 - V3, V3 = GND) (IIN = 15 mA; Pins 1 & 4 Open) (VILC = V2 - V3, V3 = GND) (IIN = -10 mA) Input Current Bridge Diode Forward Voltage Logic Low Output Voltage Logic High Output Current Logic Low Supply Current Logic High Supply Current Input Capacitance (VIN = V2 - V3 = 5.0 V) (Pins 1 & 4 Open) (IIN = 3 mA) (IIN = 3 mA) (VCC = 4.5 V; IOL = 4.2 mA) (Note 5) (Note 5) (VOH = VCC = 18 V) (V2 - V3 = 5.0 V; VO = Open) (VCC = 5 V) (VCC = 18 V; VO = Open) (f = 1 MHz; VIN = 0V) (Pins 2 & 3, Pins 1 & 4 Open) Symbol ITH+ ITHVTH+ Min 1.96 1.00 3.35 Typ 2.4 1.2 3.8 Max 3.11 1.62 4.05 Unit mA mA V
DC (Pins 2,3)
VTH-
2.01
2.5
2.86
V
Input Threshold Voltage AC (Pins 1,4)
VTH+
4.23
5.0
5.50
V
VTHIHYS VHYS VIHC1
2.87
3.7
4.20
V
Hysteresis
1.2 1.3 5.4 6.3 6.6
mA V V
Input Clamp Voltage
VIHC2 VIHC3 VILC IIN VD1,2 VD3,4 VOL IOH ICCL ICCH CIN
6.1
7.0
7.3
V
12.5 -0.75 3.0 3.7 0.65 0.65 0.04
13.4
V V
4.4
mA V V
0.4 100
V A mA A pF
1.0 0.01 50
4 4
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Operating Temperature Operating Frequency Symbol VCC TA f Min 2 0 0 Max 18 70 4 Units V C kHz
SWITCHING CHARACTERISTICS (TA = 25C, VCC = 5 V Unless otherwise specified)
AC Characteristics Propagation Delay Time (to Output Low Level) Propagation Delay Time (to Output High Level) Output Rise Time (10-90%) Output Fall Time (90-10%) Common Mode Transient Immunity (at Output High Level) Common Mode Transient Immunity (at Output Low Level) Test Conditions (RL = 4.7 k, CL = 30 pF) (Note 6) (RL = 4.7 k, CL = 30 pF) (Note 6) (RL = 4.7 k, CL = 30 pF) (RL = 4.7 k, CL = 30 pF) (IIN = 0 mA, RL = 4.7 k) (VO min = 2.0 V, VCM = 1400 V) (Notes 7,8) (IN = 3.11 mA,RL = 4.7 k) (VO max = 0.8 V, VCM = 140 V) (Notes 7,8) Symbol TPHL TPLH tr tf |CMH| Min Typ 6.0 25.0 45 0.5 4000 Max 15 40 Unit s s s s V/s
|CML|
600
V/s
PACKAGE CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified)
Characteristics Withstand Insulation Voltage Resistance (input to output) Capacitance (input to output) Test Conditions (Relative humidity < 50%) (TA = 25C, t = 1 min) (Notes 9,10) (Note 9) (VIO = 500 Vdc) (f = 1 MHz, VIO = 0 Vdc) Symbol VISO RI-O CI-O Min 2500 1012 0.6 Typ Max Unit VRMS pF
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
NOTES
1. Derate linearly above 70C free-air temperature at a rate of 1.8 mW/C. 2. Derate linearly above 70C free-air temperature at a rate of 2.5 mW/C. 3. Derate linearly above 70C free-air temperature at a rate of 0.6 mA/C. 4. Derate linearly above 70C free-air temperature at a rate of 1.9 mW/C. 5. Logic low output level at pin 6 occurs when VINVTH+ and when VIN>VTH- once VIN exceeds VTH+. Logic high output level at pin 6 occurs when VINVTH- and when VIN2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V). (Refer to Fig.10) 8. In applications where dVcm/dt may exceed 50,000 V/s (Such as static discharge), a series resistor, RCC, should be included to protect the detector chip from destructive surge currents. The recommended value for RCC is 240 V per volt of allowable drop in VCC (between pin 8 and VCC) with a minimum value of 240 . 9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 10. The 2500 VRMS/1 min. capability is validated by a 3.0 kVRMS/1 sec. dielectric voltage withstand test. 11. AC voltage is instantaneous voltage for VTH+ & VTH-. 12. All typicals at TA = 25C, VCC = 5 V unless otherwise specified.
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
TYPICAL PERFORMANCE CURVES
Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage
ICCL - LOGIC LOW SUPPLY CURRENT (mA)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -5 0.0 4 6 8 10 12 14 16 18 20 -10 0 2 4 6 8 10 12 14 50 45 DC (Pins 1,2 shorted together pins 3,4 shorted together) 40
Fig. 2 Input Current vs. Input Voltage
IIN - INPUT CURRENT (mA)
DC (Pins 1 & 4 Open)
35 30 25 20 15 10 5 0 AC (pins 2 & 3 Open)
VCC - OPERATING SUPPLY VOLTAGE (V)
VIN - INPUT VOLTAGE (V)
Fig. 3 Input Current/Low Level Output Voltage vs. Temperature
4.2 4.0 3.8 120 4.2
Fig. 4 Current Threshold/Voltage Threshold vs. Temperature
3.2
VTH(DC) - VOLTAGE THRESHOLD (V)
110 100 90 IIN VIN = 5.0 V (PINS 2 and 3) VCC = 5.0 V 80 70 60 50 40 VOL VCC = 5.0 V IOL = 4.2 mA 30 20 10 -20 0 25 45 65 0 85
3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 -40 -20 0 25 45 65 85 ITHVTHITH+ VTH+
2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8
Input Current, IIN (mA)
3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 -40
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
Fig. 5 Propagation Delay vs. Temperature
70 100 90 60 80
Fig. 6 Rise and Fall Time vs. Temperature
0.8 0.7 0.6
TP - PROPAGATION DELAY (s)
Tf
Tr - RISE TIME (s)
40 TPLH 30 TPHL 20
60 50 40 30
0.5 0.4 0.3 0.2
20 10 10 0 -60 0 -40 Tr 0.1 0.0 -20 0 25 45 65 85
-40
-20
0
20
40
60
80
100
TA - TEMPERATURE (C)
TA - TEMPERATURE (C)
(c) 2003 Fairchild Semiconductor Corporation
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Tf - FALL TIME (s)
50
70
ITH(DC) - CURRENT THRESHOLD (mA)
4.0
3.0
VOL (mV)
AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
Fig. 7 Logic High Supply Current vs. Temperature
1000
Fig. 8 External Threshold Characteristics V+/V- vs. Rx
V+/V- -EXTERNAL THRESHOLD VOLTAGE (V)
300 V+ (AC) 250 V- (AC)
ICCH - LOGIC HIGH SUPPLY CURRENT (nA)
VCC = 18 V VO = OPEN IIN = 0 mA
100
200 V+ (DC)
150
10
100
V- (DC)
50
1 -60
0 0 40 80 120 160 200 240
-40
-20
0
20
40
60
80
100
TA - TEMPERATURE (C)
RX - EXTERNAL SERIES RESISTOR (K)
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
+5V 5V 1 AC Pulse Generator tr = 5ns Z O= 50 2 DC+ 3 DC4 AC VO VCC 8 7 6 .1uf bypass RL Output (VO ) Output (VO ) 90% 10% 10% 90% 1.5 V VOL tr tf Input (VIN) t PHL t PLH VO 2.5V 0V
GND 5
VIN Pulse Amplitude = 50 V Pulse Width = 1 ms f = 100 Hz Tr = Tf = 1.0 s (10 - 90%)
Fig. 9. Switching Test Circuit
VCM H
I IN RCC * 1 AC A B 2 DC+ 3 DCVO 7 6 VCC 8 .1uf bypass RL +5V
VCM L
VCM
Output (VO ) CL**
5V
VFF
4 AC
GND 5
VO Switching Pos. (A) I IN = 0 mA VO (Min)
5V CM H
+
VCM * SEE NOTE 8
Pulse Gen VO (Max)
** CL IS 30 pF, WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE
VO
Switching Pos. (B) I IN = 3.11 mA
VOL CML
Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
Package Dimensions (Through Hole) Package Dimensions (Surface Mount)
0.390 (9.91) 0.370 (9.40)
4
4 3 2 1
PIN 1 ID.
3
2
1
PIN 1 ID.
0.270 (6.86) 0.250 (6.35)
5 6 7 8
0.270 (6.86) 0.250 (6.35)
0.390 (9.91) 0.370 (9.40)
5
6
7
8
SEATING PLANE
0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.020 (0.51) MIN
0.070 (1.78) 0.045 (1.14) 0.020 (0.51) MIN
0.300 (7.62) TYP 0.016 (0.41) 0.008 (0.20)
0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 15 MAX 0.300 (7.62) TYP
0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP Lead Coplanarity : 0.004 (0.10) MAX
0.045 [1.14] 0.315 (8.00) MIN 0.405 (10.30) MIN
Package Dimensions (0.4"Lead Spacing)
NOTE All dimensions are in inches (millimeters)
4
3
2
1
PIN 1 ID.
0.270 (6.86) 0.250 (6.35)
5
6
7
8
0.390 (9.91) 0.370 (9.40)
SEATING PLANE
0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.004 (0.10) MIN
0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 0 to 15 0.400 (10.16) TYP
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
ORDERING INFORMATION
Order Entry Identifier .S .SD .W
Option S SD W
Description Surface Mount Lead Bend Surface Mount; Tape and reel 0.4" Lead Spacing
MARKING INFORMATION
1
3700 V
3 4
2 6
XX YY T1
5
Definitions
1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) Two digit year code, e.g., `03' Two digit work week ranging from `01' to `53' Assembly package code
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
QT Carrier Tape Specifications ("D" Taping Orientation)
12.0 0.1 4.0 0.1 4.0 0.1 O1.55 0.05 1.75 0.10
4.90 0.20
0.30 0.05
7.5 0.1 13.2 0.2 16.0 0.3 10.30 0.20
0.1 MAX
10.30 0.20
O1.6 0.1
User Direction of Feed
Reflow Profile
300 Temperature (C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 225 C peak
215 C, 10-30 s
Time above 183C, 60-150 sec Ramp up = 3C/sec 3.5 4 4.5
Time (Minute) * Peak reflow temperature: 225C (package surface temperature) * Time of temperature higher than 183C for 60-150 seconds * One time soldering reflow is recommended
(c) 2003 Fairchild Semiconductor Corporation
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AC/DC TO LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) 2003 Fairchild Semiconductor Corporation
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11/8/04

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